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? semiconductor components industries, llc, 2013 march, 2013 ? rev. p1 1 publication order number: ncp1254/d ncp1254 product preview current-mode pwm controller for off-line power supplies featuring peak power excursion the ncp1254 is a highly integrated pwm controller capable of delivering a rugged and high performance offline power supply in a tsop ? 6 package. with a supply range up to 35 v, the controller hosts a jittered 65 ? khz switching circuitry operated in peak current mode control. when the power on the secondary side starts to decrease, the controller automatically folds back its switching frequency down to a minimum level of 26 khz. as the power further goes down, the part enters skip cycle while freezing the peak current setpoint. to help building rugged converters, the controller features several key protective features: a non ? dissipative over power protection for a constant maximum output current regardless of the input voltage, two latched over voltage protection inputs ? either through a dedicated pin or via the v cc input and a dual ? level auto ? recovery/latched overload/ short ? circuit timer. the controller architecture is designed to authorize a transient peak power excursion when the current setpoint hits the limit. at this point, the switching frequency is increased from 65 khz to 130 khz until the peak event disappears. the timer duration is then modulated as the converter crosses a peak power excursion mode (long) or undergoes a short circuit (short). features ? 65 ? khz fixed ? frequency current ? mode control operation with 130 ? khz excursion ? internal and adjustable over power protection (opp) circuit ? frequency foldback down to 26 khz and skip ? cycle in light load conditions ? adjustable slope compensation ? internally fixed 4 ? ms soft ? start ? fixed timer ? based auto ? recovery overload/short ? circuit protection ? 100% to 25% timer reduction from overload to short ? circuit fault ? double v cc hiccup for a reduced average power in fault mode ? frequency jittering in normal and frequency foldback modes ? latched ovp input for improved robustness and latched ovp on v cc ? up to 35 ? v v cc maximum rating ? extremely low no ? load standby power ? this is a pb ? free device typical applications ? converters requiring peak ? power capability such as printers power supplies, ac ? dc adapters for game stations. this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. pin connections 1 3 cs gnd 2 opp/latch 4 drv 6 (top view) 5 v cc tsop ? 6 case 318g style 13 marking diagram fb http://onsemi.com (note: microdot may be in either location) 1 54xayw 1 54 = specific device code x = a or b a = assembly location y = year w = work week = pb ? free package see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information
ncp1254 http://onsemi.com 2 figure 1. typical application schematic 1 2 3 6 4 5 ncp1254 vbulk . . ramp comp. opp vout ovp . table 1. pin function description pin no. pin name function description 1 gnd ? the controller ground. 2 fb feedback pin hooking an optocoupler collector to this pin will allow regula- tion via peak current mode control or frequency modulation in high ? power conditions. 3 opp/ovp adjust the over power protection latches off the part a resistive divider from the auxiliary winding to this pin sets the opp compensation level. when brought above 3 v, the part is fully latched off. 4 cs current sense + ramp compensation this pin monitors the primary peak current but also offers a means to introduce slope compensation. 5 v cc supplies the controller ? protects the ic this pin is connected to an external auxiliary voltage. an ovp comparator monitors this pin and offers a means to latch the converter in fault conditions. 6 drv driver output the driver?s output to an external mosfet gate. table 2. options and ordering information controller frequency ocp latched ocp auto ? recovery NCP1254ASN65T1G 65 khz yes no ncp1254bsn65t1g 65 khz no yes
ncp1254 http://onsemi.com 3 figure 2. internal circuit architecture s r q 65 khz clock jitter mod. vcc drv vcc and logic management vdd power on reset rramp leb vdd rfb / 4 4 ms ss power on reset gnd cs fb 600 ? ns time constant opp frequency foldback vskip vlatch the soft ? start is ? the startup sequence ? the auto ? recovery burst mode + vlimit vopp vlimit + vopp vfold s r q clamp blanking up counter 4 double hiccup rst ovp gone? 250 mv peak current freeze vfb < 1 v ? setpoint = 250 mv uvlo vsc option latch/ar vcc vovp vcc sc ip flag sc frequency increase to 130 khz vfswp rlimit ipflag, vref 100% to 25% change pon reset q 20 s q 1 ? s activated during:
ncp1254 http://onsemi.com 4 table 3. maximum ratings table symbol rating value unit v cc power supply voltage, v cc pin, continuous voltage ? 0.3 to 35 v maximum voltage on low ? power pins cs, fb and opp ? 0.3 to 10 v v drv maximum voltage on drive pin ? 0.3 to v cc +0.3 v iopp maximum injected current into the opp pin ? 2 ma i scr maximum continuous current into the v cc pin while in latched mode 3 ma r j ? a thermal resistance junction ? to ? air 360 c/w t j,max maximum junction temperature 150 c iscr maximum continuous current into v cc pin when latched 3 ma storage temperature range ? 60 to +150 c hbm human body model esd capability (all pins except hv) per jedec jesd22 ? a114f 2 kv mm machine model esd capability (all pins except drv) per jedec jesd22 ? a115c 200 v cdm charged ? device model esd capability per jedec jesd22 ? c101e 500 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78. table 4. electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) symbol rating pin min typ max unit supply section vcc on v cc increasing level at which driving pulses are authorized 5 15.8 18 20 v vcc (min) v cc decreasing level at which driving pulses are stopped 5 8 8.8 9.4 v vcc hyst hysteresis vcc on ? vcc (min) 5 6 ? ? v v zener clamped v cc when latched off @ icc = 500 a 5 ? 7 ? v icc1 start ? up current 5 ? ? 15 a icc2 internal ic consumption with v fb = 3.2 v, f sw = 65 khz and c l = 0 5 ? 1.4 2.2 ma icc3 internal ic consumption with v fb = 3.2 v, f sw = 65 khz and c l = 1 nf 5 ? 2.1 3.0 ma icc4 internal ic consumption with v fb = 4.5 v, f sw = 130 khz and c l = 0 5 ? 1.7 2.5 ma icc5 internal ic consumption with v fb = 4.5 v, f sw = 130 khz and c l = 1 nf 5 ? 3.1 4.0 ma iccstby internal ic consumption while in skip mode (v cc = 12 v, driving a typical 6 ? a/600 ? v mosfet) 750 a icc latch current flowing into v cc pin that keeps the controller latched: t j = ? 40 c to 125 c 5 40 a r lim scr current ? limit series resistor 5 4 k drive output t r output voltage rise ? time @ cl = 1 nf, 10 ? 90% of output signal 6 ? 40 ? ns t f output voltage fall ? time @ cl = 1 nf, 10 ? 90% of output signal 6 ? 30 ? ns r oh source resistance 6 ? 13 ? r ol sink resistance 6 ? 6 ? i source peak source current, v gs = 0 v (note 2) 6 300 ma i sink peak sink current, v gs = 12 v (note 2) 6 500 ma 2. guaranteed by design 3. see characterization table for linearity over negative bias voltage ? we recommend keeping the level on pin 3 below ? 300 mv. 4. a 1 ? m resistor is connected from pin 4 to the ground for the measurement.
ncp1254 http://onsemi.com 5 table 4. electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) symbol unit max typ min pin rating drive output v drvlow drv pin level at v cc close to vcc (min) with a 33 ? k resistor to gnd 6 8 ? ? v v drvhigh drv pin level at v cc = v ovp ? 0.2 v ? drv unloaded 6 10 12 14 v current comparator i ib input bias current @ 0.8 v input level on pin 4 4 0.02 a v limit1 maximum internal current setpoint ? tj = 25 c ? pin 3 grounded 4 0.744 0.8 0.856 v v limit2 maximum internal current setpoint ? tj from ? 40 to 125 c ? pin 3 grounded 4 0.72 0.8 0.88 v v foldi default internal voltage set point for frequency foldback trip point 59% of v limit 4 475 mv v freezei internal peak current setpoint freeze ( 31% of v limit ) 4 250 mv t del propagation delay from current detection to gate off ? state 4 100 150 ns t leb leading edge blanking duration 4 300 ns tss internal soft ? start duration activated upon startup, auto ? recovery ? 4 ms ioppo setpoint decrease for pin 3 biased to ?250 mv (note 3) 4 31.3 % ioopv voltage setpoint for pin 3 biased to ? 250 mv (note 3), t j = 25 c 4 0.51 0.55 0.6 v ioopv voltage setpoint for pin 3 biased to ? 250 mv (note 3), tj from ? 40 to 125 c 4 0.5 0.55 0.62 v iopps setpoint decrease for pin 3 grounded 4 0 % internal oscillator f osc,nom oscillation frequency, v fb < v fbtrans , pin 3 grounded ? 61 65 71 khz v fbtrans feedback voltage above which f sw increases ? 3.2 v f osc,max maximum oscillation frequency for v fb above v fbmax ? 120 130 140 khz v fbmax feedback voltage above which f sw is constant ? 3.8 4.1 4.2 v d max maximum duty ratio ? 76 80 84 % f jitter frequency jittering in percentage of f osc ? 5 % f swing swing frequency over the whole frequency range ? 240 hz feedback section r up internal pull ? up resistor 2 15 k r eq equivalent ac resistor from fb to gnd 2 13 k i ratio pin 2 to current setpoint division ratio ? 4 v freezef feedback voltage below which the peak current is frozen 2 1 v frequency foldback v foldf frequency foldback level on the feedback pin ? 59% of maximum peak current ? 1.9 v f trans transition frequency below which skip ? cycle occurs ? 22 26 30 khz v fold,end end of frequency foldback feedback level, f sw = f min 1.5 v v skip skip ? cycle level voltage on the feedback pin ? 400 mv skip hysteresis hysteresis on the skip comparator (note 2) ? 30 mv 2. guaranteed by design 3. see characterization table for linearity over negative bias voltage ? we recommend keeping the level on pin 3 below ? 300 mv. 4. a 1 ? m resistor is connected from pin 4 to the ground for the measurement.
ncp1254 http://onsemi.com 6 table 4. electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) symbol unit max typ min pin rating internal slope compensation v ramp internal ramp level @ 25 c (note 4) 4 2.5 v r ramp internal ramp resistance to cs pin 4 20 k protections v latch latching level input 3 2.7 3 3.3 v t latch ? blank blanking time after drive turn off 3 1 s t latch ? count number of clock cycles before latch confirmation ? 4 t latch ? del ovp detection time constant 3 600 ns timer 1 default ? overload fault timer duration ? 160 208 270 ms timer 2 default ? fault timer duration when v fb > 4.1 v is timer 1 /4 ? 40 52 68 ms v sc feedback voltage beyond which a short ? circuit is considered 2 3.9 4.1 4.3 v v ovl feedback voltage beyond which an over load is considered ? opp pin is grounded 2 3.2 v v ovp(regular) latched over voltage protection on the v cc rail 5 30.7 32.3 34 v v ovp(copack) latched over voltage protection on the v cc rail 5 26 27.5 29 v t ovp ? del delay before ovp on v cc confirmation 5 20 s 2. guaranteed by design 3. see characterization table for linearity over negative bias voltage ? we recommend keeping the level on pin 3 below ? 300 mv. 4. a 1 ? m resistor is connected from pin 4 to the ground for the measurement.
ncp1254 http://onsemi.com 7 typical characteristics figure 3. figure 4. junction temperature ( c) junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 600 650 700 750 800 850 900 125 100 75 50 25 0 ? 25 ? 50 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 figure 5. figure 6. junction temperature ( c) junction temperature ( c) 5 10 15 20 25 30 35 40 2 4 6 8 10 12 14 figure 7. figure 8. junction temperature ( c) junction temperature ( c) 8.5 9.0 9.5 10 125 100 75 50 25 0 ? 25 ? 50 10.0 10.5 11.0 11.5 12.0 12.5 13.0 14.0 i ccstby ( a) i cc@30v (ma) i cc(latch1) ( a) r ol ( ) v drvl (v) v drvh (v) 125 100 75 50 25 0 ? 25 ? 50 125 100 75 50 25 0 ? 25 ? 50 8.0 125 100 75 50 25 0 ? 25 ? 50 13.5
ncp1254 http://onsemi.com 8 typical characteristics figure 9. figure 10. junction temperature ( c) junction temperature ( c) 0.72 0.74 0.76 0.78 0.80 0.82 0.84 0.88 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 figure 11. figure 12. junction temperature ( c) junction temperature ( c) 0.20 0.22 0.24 0.26 0.28 0.30 125 100 75 50 25 0 ? 25 ? 50 200 220 260 280 320 340 380 400 figure 13. figure 14. junction temperature ( c) junction temperature ( c) 24.98 26.98 28.98 30.98 32.98 34.98 36.98 0.50 0.52 0.54 0.56 0.58 0.60 0.62 v ilim1 (v) v fold(cs) (v) v freeze(cs) (v) t leb (ns) i oppo (%) i oppv (v) 125 100 75 50 25 0 ? 25 ? 50 0.86 125 100 75 50 25 0 ? 25 ? 50 125 100 75 50 25 0 ? 25 ? 50 240 300 360 125 100 75 50 25 0 ? 25 ? 50 125 100 75 50 25 0 ? 25 ? 50
ncp1254 http://onsemi.com 9 typical characteristics figure 15. figure 16. junction temperature ( c) junction temperature ( c) 60.308 62.308 64.308 66.308 68.308 70.308 116.829 121.829 126.829 131.829 136.829 figure 17. figure 18. junction temperature ( c) junction temperature ( c) 76 77 78 79 80 81 83 84 125 100 75 50 25 0 ? 25 ? 50 10.0 11.0 11.5 12.0 12.5 13.5 14.5 15.0 figure 19. figure 20. junction temperature ( c) junction temperature ( c) 3.7 3.8 3.9 4.0 4.1 4.2 4.3 f osc(nom) (khz) f osc(max) (khz) d max (%) r upper (k ) i ratio (v/v) v freeze (fb) (v) 125 100 75 50 25 0 ? 25 ? 50 125 100 75 50 25 0 ? 25 ? 50 125 100 75 50 25 0 ? 25 ? 50 82 10.5 13.0 14.0 125 100 75 50 25 0 ? 25 ? 50 0.85 0.90 0.95 1.00 1.05 1.10 1.15 125 100 75 50 25 0 ? 25 ? 50
ncp1254 http://onsemi.com 10 typical characteristics figure 21. figure 22. junction temperature ( c) junction temperature ( c) 22 23 24 25 26 27 29 30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 figure 23. figure 24. junction temperature ( c) junction temperature ( c) 350 360 370 380 390 400 410 450 12 14 16 18 22 24 26 28 figure 25. figure 26. junction temperature ( c) junction temperature ( c) 2.7 2.8 2.9 3.0 3.1 3.2 3.3 f trans (khz) v fold_end (fb) (v) v skip (mv) r ramp (k ) v latch (v) timer1 (ms) 125 100 75 50 25 0 ? 25 ? 50 28 125 100 75 50 25 0 ? 25 ? 50 125 100 75 50 25 0 ? 25 ? 50 20 125 100 75 50 25 0 ? 25 ? 50 420 430 440 125 100 75 50 25 0 ? 25 ? 50 350 400 450 500 550 600 650 125 100 75 50 25 0 ? 25 ? 50
ncp1254 http://onsemi.com 11 typical characteristics figure 27. figure 28. junction temperature ( c) junction temperature ( c) 88 98 108 118 128 138 148 158 30.7 31.2 31.7 32.2 32.7 33.2 33.7 timer2 (ms) v ovp (v) 125 100 75 50 25 0 ? 25 ? 50 125 100 75 50 25 0 ? 25 ? 50
ncp1254 http://onsemi.com 12 application information introduction the ncp1254 implements a standard current mode architecture where the switch ? off event is dictated by the peak current setpoint. this component represents the ideal candidate where low part ? count and cost effectiveness are the key parameters, particularly in low ? cost ac ? dc adapters, open ? frame power supplies etc. the ncp1254 brings all the necessary components normally needed in today modern power supply designs, bringing several enhancements such as a non ? dissipative opp or peak power excursion for loads exhibiting variations over time. ? current ? mode operation with internal slope compensation: implementing peak current mode control at a fixed 65 ? khz frequency, the ncp1254 offers an internal slope compensation signal that can easily by summed up to the sensed current. sub harmonic oscillations can thus be compensated via the inclusion of a simple resistor in series with the current ? sense information. ? frequency excursion: when the power demand forces the peak current setpoint to reach the internal limit (0.8 v/r sense typically), the frequency is authorized to increase to let the converter deliver more power. the frequency excursion stops when 130 khz are reached at a level of 4 v. this excursion can only be temporary and its duration is set by the overload timer. ? internal opp: by routing a portion of the negative voltage present during the on ? time on the auxiliary winding to the dedicated opp pin (pin 3), the user has a simple and non ? dissipative means to alter the maximum peak current setpoint as the bulk voltage increases. if the pin is grounded, no opp compensation occurs. if the pin receives a negative voltage down to ?250 mv, then a peak current reduction down to 31.3% typical can be achieved. for an improved performance, the maximum voltage excursion on the sense resistor is limited to 0.8 v. ? low startup current: reaching a low no ? load standby power always represents a difficult exercise when the controller draws a significant amount of current during start ? up. thanks to its proprietary architecture, the ncp1254 is guaranteed to draw less than 15 a maximum, easing the design of low standby power adapters. ? emi jittering: an internal low ? frequency modulation signal varies the pace at which the oscillator frequency is modulated. this helps spreading out energy in conducted noise analysis. to improve the emi signature at low power levels, the jittering will not be disabled in frequency foldback mode (light load conditions). ? frequency foldback capability: a continuous flow of pulses is not compatible with no ? load/light ? load standby power requirements. to excel in this domain, the controller observes the feedback pin and when it reaches a level of 1.9 v, the oscillator then starts to reduce its switching frequency as the feedback level continues to decrease. when the feedback level reaches 1.5 ? v, the frequency hits its lower stop at 26 khz. when the feedback pin goes further down and reaches 1 v, the peak current setpoint is internally frozen. below this point, if the power continues to drop, the controller enters classical skip ? cycle mode. ? internal soft ? start: a soft ? start precludes the main power switch from being stressed upon start ? up. in this controller, the soft ? start is internally fixed to 4 ms. soft ? start is activated when a new startup sequence occurs or during an auto ? recovery hiccup. ? ovp input: the ncp1254 includes a latch input (pin 3) that can be used to sense an overvoltage condition on the adapter. if this pin is brought higher than the internal reference voltage v latch , then the circuit permanently latches off. the v cc pin is pulled down to a fixed level, keeping the controller latched. the latch reset occurs when the user disconnects the adapter from the mains and lets the v cc falls below the v cc reset. ? v cc ovp: a latched ovp protects the circuit against v cc runaways. the fault must be present at least 20 s to be validated. when it happens, all pulses are stopped and the v cc is permanently brought to around 7 v via an internal zener ? based scr. reset occurs when the latch current goes below icc latch . ? short ? circuit protection: short ? circuit and especially over ? load protections are difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer (the aux winding level does not properly collapse in presence of an output short). here, every time the internal 0.8 ? v maximum peak current limit is activated (or less when opp is used), an error flag is asserted and a time period starts, thanks to the internal timer. the controller can distinguish between two faulty situations: ? there is an extra demand of power, still within the power supply capabilities. in that case, the feedback level is in the vicinity of 3.2 ? 4 v (max peak current is 0.8 v, no opp). the timer duration is then 100% of its internally programmed value. if the fault disappears, e.g. the peak current no longer hits the limit, the timer is reset. ? the output is frankly shorted. the feedback level is thus pushed to its upper stop (4.5 v) and the timer is reduced to 25% of its normal value. when it elapses, protection occurs. ? in either mode, when the fault is validated, all pulses are stopped and the controller enters an auto ? recovery burst mode, with a soft ? start
ncp1254 http://onsemi.com 13 sequence at the beginning of each cycle. please note the presence of a divider by two which ignores one hiccup cycle over two (double hiccup type of burst). ? as soon as the fault disappears, the smps resumes operation. please note that some version offers an auto ? recovery mode as we just described, some do not and latch off in case of a short circuit. start ? up sequence the ncp1254 start ? up voltage is made purposely high to permit large energy storage in a small v cc capacitor value. this helps to operate with a small start ? up current which, together with a small v cc capacitor, will not hamper the start ? up time. to further reduce the standby power, the start ? up current of the controller is extremely low, below 15 a. the start ? up resistor can therefore be connected to the bulk capacitor or directly to the mains input voltage if you wish to save a few more mw. r1 200 k r2 100 k r3 100 k c1 d1 1n4007 d2 1n4007 d3 1n4007 d4 1n4007 cbulk input mains d5 1n4935 c3 d6 1n4148 vcc aux. figure 29. the startup resistor can be connected to the input mains for further power dissipation reduction. 4.7 f47 f 22 f the first step starts with the calculation of the needed v cc capacitor which will supply the controller until the auxiliary winding takes over. experience shows that this time t 1 can be between 5 and 20 ms. considering that we need at least an energy reservoir for a t 1 time of 10 ms, the v cc capacitor must be larger than: cv cc i cc t 1 vcc on vcc min 3m 10 m 9 3.3 f (eq. 1) let us select a 4.7 ? f capacitor at first and experiments in the laboratory will let us know if we were too optimistic for t 1 . the v cc capacitor being known, we can now evaluate the charging current we need to bring the v cc voltage from 0 to the vcc on of the ic, 18 v typical. this current has to be selected to ensure a start ? up at the lowest mains (85 v rms) to be less than 3 s (2.5 s for design margin): i charge vcc on c vcc 2.5 18 4.7 2.5 34 a (eq. 2) if we account for the 15 a that will flow inside the controller, then the total charging current delivered by the start ? up resistor must be 49 a. if we connect the start ? up network to the mains (half ? wave connection then), we know that the average current flowing into this start ? up resistor will be the smallest when v cc reaches the vcc on of the controller: i cvcc,min v ac,rms 2 vcc on r start ? up (eq. 3) to make sure this current is always greater than 49 a, the maximum value for r start ? up can be extracted: r start ? up v ac,rms 2 ? vcc on i cvcc , min 85 1.414 ? 18 49 413 k (eq. 4) this calculation is purely theoretical, considering a constant charging current. in reality, the take over time can be shorter (or longer!) and it can lead to a reduction of the v cc capacitor. this brings a decrease in the charging current and an increase of the start ? up resistor, for the benefit of standby power. laboratory experiments on the prototype are thus mandatory to fine tune the converter. if we chose the 400 ? k resistor as suggested by equation 4, the dissipated power at high line amounts to: v ac,peak 2 4r start ? up 230 2 2 4 400 k 105 k 1.6 meg 66 mw (eq. 5) p rstartup,max
ncp1254 http://onsemi.com 14 now that the first v cc capacitor has been selected, we must ensure that the self ? supply does not disappear when in no ? load conditions. in this mode, the skip ? cycle can be so deep that refreshing pulses are likely to be widely spaced, inducing a large ripple on the v cc capacitor. if this ripple is too large, chances exist to touch the vcc min and reset the controller into a new start ? up sequence. a solution is to grow this capacitor but it will obviously be detrimental to the start ? up time. the option offered in figure 29 elegantly solves this potential issue by adding an extra capacitor on the auxiliary winding. however, this component is separated from the v cc pin via a simple diode. you therefore have the ability to grow this capacitor as you need to ensure the self ? supply of the controller without affecting the start ? up time and standby power. triggering the scr the latched ? state of the ncp1254 is maintained via an internal thyristor (scr). when the voltage on pin 3 exceeds the latch voltage for four consecutive clock cycles, the scr is fired and immediately stops the output pulses. the same scr is fired when an ovp is sensed on the v cc pin. when this happens, all pulses are stopped and v cc is discharged to a fix level of 7 v typically: the circuit is latched and the converter no longer delivers pulses. to maintain the latched ? state, a permanent current must be injected in the part. if too low of a current, the part de ? latches and the converter r esumes operation. this current is characterized to 32 a as a minimum but we recommend to include a design margin and select a value around 60 a. the test is to latch the part and reduce the input voltage until it de ? latches. if you de ? latch at v in = 70 v rms for a minimum voltage of 85 v rms, you are fine. if it precociously recovers, you will have to increase the start ? up current, unfortunately to the detriment of standby power. the most sensitive configuration is actually that of the half ? wave connection proposed in figure 29. as the current disappears 5 ms for a 10 ? ms period (50 ? hz input source), the latch can potentially open at low line. if you really reduce the start ? up current for a low standby power design, you must ensure enough current in the scr in case of a faulty event. an alternate connection to the above is shown below (figure 30): l1 n vcc 1 meg 1 meg figure 30. the full ? wave connection ensures latch current continuity as well as x2 ? discharge path. in this case, the current is no longer made of 5 ? ms ?holes? and the part can be maintained at a low input voltage. experiments show that these 2 ? m resistor help to maintain the latch down to less than 50 v rms, giving an excellent design margin. standby power with this approach was also improved compared to figure 29 solution. please note that these resistors also ensure the discharge of the x2 ? capacitor up to a 0.47 ? f type. the de ? latch of the scr occurs when the injected current in the v cc pin falls below the minimum stated in the data ? sheet (32 a at room temp). internal over power protection there are several known ways to implement over power protection (opp), all suffering from particular problems. these problems range from the added consumption burden on the converter or the skip ? cycle disturbance brought by the current ? sense offset. a way to reduce the power capability at high line is to capitalize on the negative voltage swing present on the auxiliary diode anode. during the turn ? on time, this point dips to ? nv in , n being the turns ratio between the primary winding and the auxiliary winding. the negative plateau observed on figure 31 will have an amplitude depending on the input voltage. the idea implemented in this chip is to sum a portion of this negative swing with the 0.8 ? v internal reference level. for instance, if the voltage swings down to ? 150 mv during the on ? time, then the internal peak current set point will be fixed to 0.8 ? 0.150 = 650 mv. the adopted principle appears in figure 32 and shows how the final peak current set point is constructed.
ncp1254 http://onsemi.com 15 464u 472u 480u 488u 496u time in seconds ? 40.0 ? 20.0 0 20.0 40.0 v(24) in volts plot1 figure 31. the signal obtained on the auxiliary winding swings negative during the on ? time. off ? time on ? time n 1 (v out + v f ) ? n 2 v bulk let?s assume we need to reduce the peak current from 2.5 a at low line, to 2 a at high line. this corresponds to a 20% reduction or a set point voltage of 640 mv. to reach this level, then the negative voltage developed on the opp pin must reach: v opp 640 m 800 m ? 160 mv (eq. 6) vdd ref opp + ? from fb reset cs vcc aux roppu swings to: vout during toff ? nvin during ton iopp roppl sum2 k1 k2 0.8 v ref = 0.8 v + vopp (vopp is negative) this point will be adjusted to reduce the ref at hi line to the desired level. figure 32. the opp circuitry affects the maximum peak current set point by summing a negative voltage to the internal voltage reference. 5%
ncp1254 http://onsemi.com 16 let us assume that we have the following converter characteristics: v out = 19 v v in = 85 to 265 v rms n 1 = n p :n s = 1:0.25 n 2 = n p :n aux = 1:0.18 given the turns ratio between the primary and the auxiliary windings, the on ? time voltage at high line (265 vac) on the auxiliary winding swings down to: v aux ? n 2 v in,max ? 0.18 375 ? 67.5 v (eq. 7) to obtain a level as imposed by equation 6, we need to install a divider featuring the following ratio: div 0.16 67.5
2.4 m (eq. 8) if we arbitrarily fix the pull ? down resistor r oppl to 1 k , then the upper resistor can be obtained by: r oppu 67.5 0.16 0.16 1k
421 k (eq. 9) if we now plot the peak current set point obtained by implementing the recommended resistor values, we obtain the following curve (figure 33): 100% 80% peak current setpoint 375 figure 33. the peak current regularly reduces down to 20% at 375 v dc. v bulk the opp pin is surrounded by zener diodes stacked to protect the pin against esd pulses. these diodes accept some peak current in the avalanche mode and are designed to sustain a certain amount of energy. on the other side, negative injection into these diodes (or forward bias) can cause substrate injection which can lead to an erratic circuit behavior. to avoid this problem, the pin is internal clamped slightly below ?300 mv which means that if more current is injected before reaching the esd forward drop, then the maximum peak reduction is kept to 40%. if the voltage finally forward biases the internal zener diode, then care must be taken to avoid injecting a current beyond ?2 ma. given the value of r oppu , there is no risk in the present example. finally, please note that another comparator internally fixes the maximum peak current set point to 0.8 v even if the opp pin is adversely biased above 0 v. frequency foldback the reduction of no ? load standby power associated with the need for improving the efficiency, requires a change in the traditional fixed ? frequency type of operation. this controller implements a switching frequency foldback when the feedback voltage passes below a certain level, v fold , set around 1.9 v. below this point, the frequency no longer changes and the feedback level still controls the peak current setpoint. when the feedback voltage reaches 1 v, the peak current freezes to (250 mv or ?31% of the maximum 0.8 ? v setpoint). if the power continues to decrease, the part enters skip cycle at a moderate peak current for the best noise ? free performance in no ? load conditions. figure 34 depicts the adopted scheme for the part.
ncp1254 http://onsemi.com 17 figure 34. by observing the voltage on the feedback pin, the controller reduces its switching frequency for an improved performance at light load. 65 khz 26 khz 400 mv 3.2 v 0.8 v fb max min max min frequency peak current setpoint 130 khz 1.5 v v fb 1.9 v 4 v 3.2 v v fold,end v fold f sw v fb v cs 0.47 v 0.25 v v skip 0.4 v v fold 1.9 v v freeze 1 v skip auto ? recovery short ? circuit protection in case of output short ? circuit or if the power supply experiences a severe overloading situation, an internal error flag is raised and starts a countdown timer. if the flag is asserted longer than its internal value, the driving pulses are stopped and v cc falls down as the auxiliary pulses are missing. when it crosses vcc (min) , the controller consumption is down to a few a and the v cc slowly builds up again thanks to the resistive starting network. when v cc reaches vcc on , the controller purposely ignores the re ? start and waits for another v cc cycle: this is the so ? called double hiccup. by lowering the duty ratio in fault condition, it naturally reduces the average input power and the rms current in the output cable. illustration of such principle appears in figure 35. please note that soft ? start is activated upon re ? start attempt. 18 v figure 35. an auto ? recovery hiccup mode is entered in case a faulty event is acknowledged by the controller. v cc (t) v drv (t) no pulse area 8.8 v
ncp1254 http://onsemi.com 18 slope compensation the ncp1254 includes an internal ramp compensation signal. this is the buffered oscillator clock delivered during the on time only. its amplitude is around 2.5 v at the maximum authorized duty ratio. ramp compensation is a known means used to cure sub harmonic oscillations in ccm ? operated current ? mode converters. these oscillations take place at half the switching frequency and occur only during continuous conduction mode (ccm) with a duty ratio greater than 50%. to lower the current loop gain, one usually mixes between 50 and 100% of the inductor downslope with the current ? sense signal. figure 36 depicts how internally the ramp is generated. please note that the ramp signal will be disconnected from the cs pin, during the off ? time. rsense rcomp 20 k 0 v 2.5 v cs + ? l.e.b from fb setpoint latch reset on figure 36. inserting a resistor in series with the current sense information brings slope compensation and stabilizes the converter in ccm operation. in the ncp1254 controller, the oscillator ramp exhibits a 2.5 ? v swing reached at a 80% duty ratio. if the clock operates at a 65 ? khz frequency, then the available oscillator slope corresponds to: v ramp,peak d max t sw 2.5 0.8 15 208 kv s or 208 mv s (eq. 10) s ramp in our flyback design, let?s assume that our primary inductance l p is 770 h, and the smps delivers 19 v with a n p : n s turns ratio of 1:0.25. the off ? time primary current slope s p is thus given by: s p v out v f n p n s l p ( 19 0.8 ) 4 770 103 ka s (eq. 11) given a sense resistor of 330 m , the above current ramp turns into a voltage ramp of the following amplitude: s sense s p r sense 103k 0.33 34kv s or 34mv s (eq. 12) if we select 50% of the downslope as the required amount of ramp compensation, then we shall inject a ramp whose slope is 17 mv/ s. our internal compensation being of 208 mv/ s, the divider ratio ( divratio ) between r comp and the internal 20 k resistor is: divratio 17 m 208 m 0.082 (eq. 13) the series compensation resistor value is thus: r comp r ramp divratio 20 k 0.082
1.6 k (eq. 14) a resistor of the above value will then be inserted from the sense resistor to the current sense pin. we recommend adding a small 100 ? pf capacitor, from the current sense pin to the controller ground for improved noise immunity. please make sure both components are located very close to the controller. latching off the controller the opp pin not only allows a reduction of the peak current set point in relationship to the line voltage, it also offers a means to permanently latch ? off the part. when the part is latched ? off, the v cc pin is internally pulled down to around 7 v and the part stays in this state until the user cycles the v cc down and up again, e.g. by un ? plugging the converter from the mains outlet. the latch detection is made by observing the opp pin by a comparator featuring a 3 ? v reference voltage. however, for noise reasons and in particular to avoid the leakage inductance contribution at turn off, a 1 ? s blanking delay is introduced before the output of the ovp comparator is checked. then, the ovp
ncp1254 http://onsemi.com 19 comparator output is validated only if its high ? state duration lasts a minimum of 600 ns. below this value, the event is ignored. then, a counter ensures that 4 successive ovp events h ave occurred before actually latching the part. there are several possible implementations, depending on the needed precision and the parameters you want to control. the first and easiest solution is the additional resistive divider on top of the opp one. this solution is simple and inexpensive but requires the insertion of a diode to prevent disturbing the opp divider during the on ? time . 4 5 1 opp vlatch 10 8 9 vcc aux. winding opp roppl 1 k roppu 421 k 11 d2 1n4148 ovp r3 5 k c1 100 p figure 37. a simple resistive divider brings the opp pin above 3 v in case of a v cc voltage runaway above 18 v. first, calculate the opp network with the above equations. then, suppose we want to latch off our controller when v out exceeds 25 v. on the auxiliary winding, the plateau reflects the output voltage by the turns ratio between the power and the auxiliary windings. in case of voltage runaway for our 19 ? v adapter, the plateau will go up to: v aux,ovp 25 0.18 0.25 18 v (eq. 15) since our ovp comparator trips at a 3 ? v level, across the 1 ? k selected opp pull ? down resistor, it implies a 3 ? ma current. from 3 v to go up to 18 v, we need an additional 15 v. under 3 ma and neglecting the series diode forward drop, it requires a series resistor of: r ovp v latch v vop v ovp r oppl 18 3 3 1k 15 3m 5k (eq. 16) in nominal conditions, the plateau establishes to around 14 v. given the divide ? by ? 6 ratio, the opp pin will swing to 14/6 = 2.3 v during normal conditions, leaving 700 mv for the noise immunity. a 100 ? pf capacitor can be added to improve it and avoids erratic trips in presence of external surges. do not increase this capacitor too much otherwise the opp signal will be affected by the integrating time constant. a second solution for the ovp detection alone, is to use a zener diode wired as recommended by figure 38.
ncp1254 http://onsemi.com 20 4 5 1 opp vlatch 10 8 9 vcc aux. winding opp roppl 1 k roppu 421 k 11 d3 15 v d2 1n4148 ovp c1 22 pf figure 38. a zener diode in series with a diode helps to improve the noise immunity of the system. in this case, to still trip at a 18 ? v level, we have selected a 15 ? v zener diode. in nominal conditions, the voltage on the opp pin is almost 0 v during the off time as the zener is fully blocked. this technique clearly improves the noise immunity of the system compared to that obtained from a resistive string as in figure 37. please note the reduction of the capacitor on the opp pin to 10 ? 22 pf. this is because of the potential spike going through the zener parasitic capacitor and the possible auxiliary level shortly exceeding its breakdown voltage during the leakage inductance reset period (hence the internal 1 ? s blanking delay at turn off). this spike despite its very short time is energetic enough to charge the added capacitor c 1 and given the time constant, could make it discharge slower, potentially disturbing the blanking circuit. when implementing the zener option, it is important to carefully observe the opp pin voltage (short probe connections!) and check that enough margin exists to that respect. over temperature protection in a lot of designs, the adapter must be protected against thermal runaways, e.g. when the temperature inside the adapter box increases beyond a certain value. figure 39 shows how to implement a simple otp using an external ntc and a series diode. the principle remains the same: make sure the opp network is not bothered by the additional ntc hence the presence of this diode. when the ntc resistor will diminish as the temperature increases, the voltage on the opp pin during the off time will slowly increase and, once it crosses 3 v for 4 consecutive clock cycles, the controller will permanently latch off. opp vlatch vcc aux. winding opp roppl 2.5 k ntc d2 1n4148 roppu 841 k full latch figure 39. the internal circuitry hooked to pin 3 can be used to implement over temperature protection (otp).
ncp1254 http://onsemi.com 21 back to our 19 ? v adapter, we have found that the plateau voltage on the auxiliary diode was 13 v in nominal conditions. we have selected an ntc which offers a 470 ? k resistor at 25 c and drops to 8.8 k at 110 c. if our auxiliary winding plateau is 14 v and we consider a 0.6 ? v forward drop for the diode, then the voltage across the ntc in fault mode must be: v ntc 14 3 0.6 10.4 v (eq. 17) based on the 8.8 ? k ntc resistor at 110 c, the current inside the device must be: i ntc 10.4 8.8 k
1.2 ma (eq. 18) as such, the bottom resistor r oppl , can easily be calculated: r oppl 3 1.2 m 2.5 k (eq. 19) now that the pull ? down opp resistor is known, we can calculate the upper resistor value r oppu to adjust the power limit at the chosen output power level. suppose we need a 200 ? mv decrease from the 0.8 ? v set point and the on ? time swing on the auxiliary anode is ? 67.5 v, then we need to drop over r oppu a voltage of: v r oppu 67.5 0.2 67.3 v (eq. 20) the current circulating in the pull down resistor r oppl in this condition will be: i r oppl 200 m 2.5 k 80 a (eq. 21) the r oppu value is therefore easily derived: r oppu 67.3 80 841 k (eq. 22) combining ovp and otp the otp and zener ? based ovp can be combined together as illustrated by figure 40. 4 5 1 opp vlatch 10 8 9 vcc aux. winding opp roppl 2.5 k 11 ntc d2 1n4148 roppu 841 k d3 15 v ovp figure 40. with the ntc back in place, the circuit nicely combines ovp, otp and opp on the same pin in nominal v cc /output conditions, when the zener is not activated, the ntc can drive the opp pin and trigger the adapter in case of a fault. on the contrary, in nominal temperature conditions, if the loop is broken, the voltage runaway will be detected and acknowledged by the controller. in case the opp pin is not used for either opp or ovp, it can simply be grounded. filtering the spikes the auxiliary winding is the seat of spikes that can couple to the opp pin via the parasitic capacitances exhibited by the zener diode and the series diode. to prevent an adverse triggering of the over voltage protection circuitry, it is possible to install a small rc filter before the detection network. typical values are those given in figure 41 and must be selected to provide the adequate filtering function without degrading the stand ? by power by an excessive current circulation.
ncp1254 http://onsemi.com 22 4 5 1 opp vlatch 10 3 9 vcc aux. winding opp roppl 2.5 k 11 ntc 2 d2 1n4148 roppu 841 k d3 15 v ovp r3 220 c1 330 pf additional filter figure 41. a small rc filter avoids the fast rising spikes from reaching the protection pin of the ncp1254 in presence of energetic perturbations superimposed on the input line. latching off with the v cc pin the ncp1254 hosts a dedicated comparator on the v cc pin. when the voltage on this pin exceeds 25.5 v typically for more than 20 s, a signal is sent to the internal latch and the controller immediately stops the driving pulses while remaining in a lockout state. the part can be reset by cycling down its v cc , for instance by pulling off the power. this technique offers a simple and cheaper means to protect the converter against optocoupler failures without using the opp pin and a zener diode. peak power excursions there are applications where the load profile heavily changes from a nominal to a peak value. for instance, it is possible that a 30 ? w ac ? dc adapter accepts power excursions up to 60 w in certain conditions. inkjet printers typically fall in that category of peak power adapters. however, to avoid growing the transformer size, an existing technique consists in freezing the peak current to a maximum value (0.8/ r sense in our case) but authorizes frequency increase to a certain point. this point is internally fixed at 130 khz. figure 42. the feedback pin modulates the frequency up to 130 khz (short ? circuit, maximum power) or down to 26 khz in frequency foldback. 4.5 3.2 peak current is clamped 65 khz maximum frequency is f osc,max 1.9 0.4 t 0 duty ? ratio 65 khz 1 peak current is frozen peak current can change 4.0 1.5 26 khz v fb (v) f sw decreases f sw increases f sw is fixed i peak max i peak min
ncp1254 http://onsemi.com 23 figure 42 shows the voltage evolution from almost 0 v to the open ? loop level, around 4.5 v. at low power levels or in no ? load operation, the feedback voltage stays in the vicinity of 400 mv and ensures skip ? cycle operation. in this mode, the peak current is frozen to 31% of its maximum value. this freeze lasts as long as v fb stays below 1 v. beyond 1 v, the peak current is authorized to follow v fb through a ratio of 4. when the power demand goes up, the switching frequency linearly increases from 26 khz up to 65 khz, a value reached when the feedback voltage exceeds 1.5 v. beyond 1.9 v, the frequency no longer changes. as v fb still increases, we are in a fixed ? frequency variable peak current mode control type of operation until the feedback voltage hits 3.2 v. at this point, the maximum current is limited to 0.8 v/ r sense . if v fb further increases, it means the converter undergoes an overload and requires more power from the source. as the peak current excursion is stopped, the only way to deliver more power is to increase the switching frequency. from 3.2 v up to 4 v, the frequency linearly increases from 65 khz to 130 khz. the maximum power delivered by the converter depends whether it operates in discontinuous conduction mode (dcm) or in continuous conduction mode (ccm): p max,dcm 1 2 l p f sw,max i peak,max 2 (eq. 23) p max,ccm 1 2 l p f sw,max i peak,max 2 i valley 2 (eq. 24) where i peak,max is the maximum peak current authorized by the controller and i valley the valley current reached just before a new switching cycle begins. this current is expressed by the following formula: i valley i peak v out v f nl p t off (eq. 25) in dcm, the valley current is equal to 0. two levels of protection once the feedback voltage asks for the maximum peak current, the controller knows that an overload condition has started. an internal timer is operated as soon as the maximum peak current setpoint is reached. its duration is internally set to 200 ms. if the feedback voltage continues its rise, it means that the converter output voltage is going down further, close to a short ? circuit situation. when the feedback voltage approaches the open ? loop level (above 4.0 v typically), the original timer duration is divided by 4. for instance, at start ? up, even if the overload timer is programmed to 200 ms, when the feedback voltage jumps above 4.0 v, the controller will wait 50 ms before fault detection occurs. of course, if the feedback does not stay that long in the region of concern, the timer is reset when returning to a normal level. figure 43 shows the timer values versus the feedback voltage. figure 43. depending on the feedback level, the timer will take two different values: it will authorize a transient overload, but will reduce a short ? circuit duration. t 4.0 3.2 open loop voltage 100% timer ? overload 25% timer ? short ? circuit 65 khz 130 khz fixed ? frequency variable peak current 26 khz skip cycle 0.4 1 4.5 max 1.9 1.5 frequency foldback variable peak current 65 khz frozen peak current frozen current fixed frequency variable peak current v fb (v) max i peak 31% max i peak
ncp1254 http://onsemi.com 24 please note that the overload situation (ovl) is detected when the maximum peak current limit is hit. it can be 3.2 v as indicated in the graph in case of no over power protection (opp). if you have programmed an opp level of ? 200 mv for instance, the ovl threshold becomes (0.8 ? 0.2) x 4 = 2.4 v. when the maximum peak current situation is lifted, the converter returns to a normal situation, the timer is reset. the short circuit situation is detected by sensing a feedback voltage beyond 3.6 v. for the sake of the explanation, we have gathered two different events in figure 44: figure 44. 4.0 v 3.2 v 4.0 v 3.2 v fault fault ovl sc sc ovl sc ovl 130 khz 65 khz 130 khz 65 khz v fb v ct v fb when the feedback voltage exits a fault region before time completion, the timer is reset. on the contrary, if the timer elapses, the part enters an auto ? recovery hiccup or latches off depending on the operated version. in the first case, the feedback is pushed to the maximum upon start ? up. the timer starts with a charging slope of the short ? circuit condition (sc). with an ovl timer internally set to 200 ms, the timer duration in this start ? up sequence is 50 ms. as soon as regulation occurs, the timer gets reset. an overload occurs shortly after (ovl). the internal timer immediately starts to count when the 3.2 ? v level is crossed (v fb with no opp). as the overload lasts less than 200 ms, the feedback returns to its regulation level and resets the timer. in the second case, the overload occurs after regulation but the feedback voltage quickly jumps into the short ? circuit area. at this point, the countdown is accelerated as the charging slope changed to a steeper one. the load goes back to an ovl mode and the counter slows down. finally, back to short circuit again and the timer trips the fault circuitry after completion: all pulses are immediately stopped and an auto ? recovery double hiccup takes places.
ncp1254 http://onsemi.com 25 package dimensions ? 6 case 318g ? 02 issue u 23 4 5 6 d 1 e b e1 a1 a 0.05 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. maximum lead thickness includes lead finish. minimum lead thickness is the minimum thickness of base material. 4. dimensions d and e1 do not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. dimensions d and e1 are determined at datum h. 5. pin one indicator must be located in the indicated zone. c *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* dim a min nom max millimeters 0.90 1.00 1.10 a1 0.01 0.06 0.10 b 0.25 0.38 0.50 c 0.10 0.18 0.26 d 2.90 3.00 3.10 e 2.50 2.75 3.00 e 0.85 0.95 1.05 l 0.20 0.40 0.60 0.25 bsc l2 ? 0 1 0 style 13: pin 1. gate 1 2. source 2 3. gate 2 4. drain 2 5. source 1 6. drain 1 1.30 1.50 1.70 e1 e recommended note 5 l c m h l2 seating plane gauge plane detail z detail z 0.60 6x 3.20 0.95 6x 0.95 pitch dimensions: millimeters m on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp1254/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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